`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    18:35:08 11/11/2011 
// Design Name: 
// Module Name:    serial_in 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module serial_out(
    input[2047:0]  din,
    input          clk,
    input          rst,
    output[31:0]   dout,
    output[5:0]    oaddr,
    output         busy
    );

reg[31:0] out_buff;
reg         is_sending;

assign dout = out_buff;
assign busy = is_sending;

reg[12:0]   index;
reg[5:0]    addr_select;

assign oaddr = addr_select;

always @(posedge clk) begin
    case(index[5:0])
         0: out_buff <= din[  31:   0];
         1: out_buff <= din[  63:  32];
         2: out_buff <= din[  95:  64];
         3: out_buff <= din[ 127:  96];
         4: out_buff <= din[ 159: 128];
         5: out_buff <= din[ 191: 160];
         6: out_buff <= din[ 223: 192];
         7: out_buff <= din[ 255: 224];
         8: out_buff <= din[ 287: 256];
         9: out_buff <= din[ 319: 288];
        10: out_buff <= din[ 351: 320];
        11: out_buff <= din[ 383: 352];
        12: out_buff <= din[ 415: 384];
        13: out_buff <= din[ 447: 416];
        14: out_buff <= din[ 479: 448];
        15: out_buff <= din[ 511: 480];
        16: out_buff <= din[ 543: 512];
        17: out_buff <= din[ 575: 544];
        18: out_buff <= din[ 607: 576];
        19: out_buff <= din[ 639: 608];
        20: out_buff <= din[ 671: 640];
        21: out_buff <= din[ 703: 672];
        22: out_buff <= din[ 735: 704];
        23: out_buff <= din[ 767: 736];
        24: out_buff <= din[ 799: 768];
        25: out_buff <= din[ 831: 800];
        26: out_buff <= din[ 863: 832];
        27: out_buff <= din[ 895: 864];
        28: out_buff <= din[ 927: 896];
        29: out_buff <= din[ 959: 928];
        30: out_buff <= din[ 991: 960];
        31: out_buff <= din[1023: 992];
        32: out_buff <= din[1055:1024];
        33: out_buff <= din[1087:1056];
        34: out_buff <= din[1119:1088];
        35: out_buff <= din[1151:1120];
        36: out_buff <= din[1183:1152];
        37: out_buff <= din[1215:1184];
        38: out_buff <= din[1247:1216];
        39: out_buff <= din[1279:1248];
        40: out_buff <= din[1311:1280];
        41: out_buff <= din[1343:1312];
        42: out_buff <= din[1375:1344];
        43: out_buff <= din[1407:1376];
        44: out_buff <= din[1439:1408];
        45: out_buff <= din[1471:1440];
        46: out_buff <= din[1503:1472];
        47: out_buff <= din[1535:1504];
        48: out_buff <= din[1567:1536];
        49: out_buff <= din[1599:1568];
        50: out_buff <= din[1631:1600];
        51: out_buff <= din[1663:1632];
        52: out_buff <= din[1695:1664];
        53: out_buff <= din[1727:1696];
        54: out_buff <= din[1759:1728];
        55: out_buff <= din[1791:1760];
        56: out_buff <= din[1823:1792];
        57: out_buff <= din[1855:1824];
        58: out_buff <= din[1887:1856];
        59: out_buff <= din[1919:1888];
        60: out_buff <= din[1951:1920];
        61: out_buff <= din[1983:1952];
        62: out_buff <= din[2015:1984];
        63: out_buff <= din[2047:2016];
    endcase
end
always @(posedge clk) begin
    if(rst) begin
        index <= 0;
        is_sending <= 1;
        addr_select <= 0;
    end
    else if(is_sending) begin
        index <= index + 1;
        addr_select <= index[11:6];
        is_sending <= ~index[12];
    end
end

endmodule
